bad synchronous description ⠀

by Surendran   Last Updated February 13, 2018 14:02 PM

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_TEXTIO.ALL;
use IEEE.numeric_std.ALL;
use std.textio.all;

entity ps_m is
port (clk_m:in std_logic;
    por:in std_logic;
        p_s:out std_logic);
end ps_m;

architecture Behavioral of ps_m is

signal temp:std_logic_vector(2 downto 0):="000";
begin

process (por,clk_m)
begin 
    if(por='1') then
       p_s<='0';
        temp<="000";
    else
    if (temp="110" and clk_m='0' and clk_m'event) then
        p_s<='1';
         temp<=temp+1;
    elsif (not(temp="110") and clk_m='0' and clk_m'event) then
         p_s<='0'; 
         temp<=temp+1;
    end if;
end if;
end process;

end Behavioral;
Tags : xilinx


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