VHDL process sensitivity list

by Mark Henderson   Last Updated June 30, 2020 02:25 AM

In my testbench i set reset=1 and then reset=0 after 1 ns In the simulation, err_count <= std_logic_vector(err_count_int); does not execute, does anyone know why? reset_out <= '1'; is also executed


library IEEE;
use IEEE.Std_logic_1164.all;
use IEEE.Numeric_Std.all;

entity controller is
    port(
            enable : in std_logic:='0';
            reset: in std_logic:='0';
            clk : in std_logic;
            eds: in std_logic:='0';
            ecs: out std_logic:='0';
            reset_out: out std_logic:='0';
            en_pipeline: out std_logic:='0';
            err_count: out std_logic_vector(4 downto 0)
        );
end controller;

architecture beh of controller is

    signal err_count_int: unsigned(4 downto 0);
    signal increment: std_logic_vector(4 downto 0):= "00001";

begin
    process(reset) begin
        if reset = '1' then 
            err_count_int <= to_unsigned (0, err_count_int'length);
            err_count <= std_logic_vector(err_count_int);
            reset_out <= '1';
        elsif reset = '0' then
            reset_out <= '0';
        end if;
    end process;
    
    -- process(clk) begin
        -- if enable = '1' and rising_edge(clk) then
            -- en_pipeline <= '1';
            -- err_count_int <= err_count_int + unsigned(increment);
            -- err_count <= std_logic_vector(err_count_int);
        -- elsif rising_edge(clk) AND eds = '1' then
            -- err_count_int <= err_count_int + 1;
            -- err_count <= std_logic_vector(err_count_int);
            -- ecs <= '1';
        -- end if;
    -- end process;
    
end beh;




```
Tags : vhdl


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