Diamond: Warning: logical net has no load

by axk   Last Updated September 18, 2019 20:25 PM

I've a Diamond project with 1 System Verilog module (using Synplify Pro for synthesiz) with the code as follows:

module arrtest(clk, led);
input clk;
output reg led = 0;

reg [3:0] arr_index = 0;
reg [7:0] intervals [0:9]  = {8'd125, 8'd128, 8'd200, 8'd210, 8'd192, 8'd192, 8'd185, 8'd100, 8'd255, 8'd80};
reg [7:0] countdown = 0;

reg initialized = 0;

always @(posedge clk)
begin   
      countdown <= countdown - 8'd1;

      if(countdown == 0)
      begin
          countdown <= intervals[arr_index];
          arr_index <= (arr_index < 3'd10) ? arr_index + 4'd1 : 4'd0;
          led <= !led;
      end   
end

endmodule

And I've receiving the following warnings at the Translate Design stage:

Running DRC...

WARNING - logical net 'countdown_cry_0_S0[0]' has no load.
WARNING - logical net 'countdown_s_0_S1[7]' has no load.
WARNING - logical net 'countdown_s_0_COUT[7]' has no load.
WARNING - DRC complete with 3 warnings.

So I'm suspecting that something's wrong in the design and a part of the design doesn't get synthesized.

On the other hand on the Map Trace stage it gives me the following:

Top 10 highest fanout non-clock nets:
Net arr_index[0]: 12 loads
Net arr_index[1]: 12 loads
Net arr_index[2]: 12 loads
Net arr_index[3]: 8 loads
Net countdown6_i: 8 loads
Net countdown: 4 loads
Net countdown[4]: 3 loads
Net countdown[5]: 3 loads
Net countdown6_3: 2 loads
Net countdown6_4: 2 loads

And I'm reading it as "the countdown net IS loaded".

Why am I getting these "has no load" warnings and do they mean that a part of the design doesn't get synthesized?

Tags : lattice synplify


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